*bldg. 2  NO.102/ 16:00~

Biography:

Gwangsun Kim is an assistant professor in the Department of Computer Science and Engineering at POSTECH. Before joining POSTECH, he was a Senior Research Engineer at Arm, where he worked on the design and evaluation of the memory system for future Arm server CPUs. His research areas include computer architecture, interconnection network, GPU computing, and memory system. His research was recognized with Best Paper Award at PACT 2013, Best Invention Award for Industry-Academia Cooperation Projects from SK Hynix in 2014, and a nomination for Best Paper Award at PACT 2016. He worked as a Research Intern at NVIDIA, Austin, TX, and Samsung Electronics, South Korea. He received his Ph.D. and M.S. degrees in Computer Science from KAIST and B.S. degree in Electronic and Electrical Engineering and Computer Science and Engineering (double major) from POSTECH.

Abstract:

Computing systems are faced with unprecedented challenges in processing a large amount of data efficiently as demanded by data-intensive applications such as big data analytics and machine learning. To achieve high system performance for such applications, it is important to remove bottlenecks that exist in current systems for memory accesses as well as communication between different processors and accelerators (e.g., GPUs). Meanwhile, recently developed 3D-stacked memory devices such as Hybrid Memory Cube not only provides high memory bandwidth but also presents new opportunities in designing system interconnect as the memories can create a memory network. In this talk, I will propose a new system interconnect design referred to as Memory-Centric Network (MCN) that leverages the memory network to address the bandwidth bottlenecks in conventional Processor-Centric Network designs. Moreover, the MCN can be extended to interconnect the memory devices from compute accelerators and host processors to create a Unified Memory Network, which addresses the PCIe bottleneck in the system while removing the need for memory copies between processors and accelerators. In addition, to overcome the processor interface bandwidth bottleneck, Near-Data Processing through the memory network will be proposed. Lastly, I will discuss future research directions in memory system based on new technologies that are currently in development.