Exploiting SW Information for Efficient Memory Hierarchy and Resource Management
Hyojin Sung is an assistant professor in computer science and engineering as POSTECH. Her research interests are computer architecture, parallel computing, and compiler/runtime technologies, focusing on systematic co-design of different layers in the SW and HW interface. She received the Ph.D. in computer science from Illinois in 2015. She earned her bachelor’s in literature and computer science from Seoul National University and the M.S. in computer science from UC San Diego. Before joining POSTECH in fall 2019, she worked as a research staff member at IBM TJ Watson research center until recently and joined POSTECH as an assistant professor this fall. She is a recipient of W.J. Poppelbaum memorial award in 2014 and a two-time winner of the Feng Chen memorial award. Her research publications include a best paper awardee and a selection to Micro Top Picks journal.
The slowing down of Moore’s law puts architectural and compiler innovations at the forefront. At the same time, the demand for performance is growing with new diverse workload in machine learning, big data analytics, and high performance computing. The key insight in my research is that systematically exploiting software information information designing SW/HW interfaces enables a performance and complexity efficient solution. However, it is challenging for such solutions to become reality, as they must work for a wide range of software without requiring too many changes to the software. I have focused on developing general-purpose and least-disruptive software-driven solutions at each layer of the SW/HW interfaces: from translating software into optimized binary (compilers), and making intelligent resource management decisions (runtime) to designing and organizing performance and complexity efficient hardware components (architecture).
Recent software research has imposed more discipline on shared-memory programs to prevent unstructured data sharing, thus making programs easier to maintain. Driven by such software evolution, I holistically re-designed a cache coherence protocol that is simpler and more energy efficient than the state-of-the-art option. The resulting system, DeNovo, uses safety guarantees and memory access information from software to address complexity, performance, and energy inefficiencies in current shared-memory systems. More recently, I focused on designing and implementing compiler and runtime solutions that exploit rich program-level information, including program structures and parallelism patterns. CogR is a machine-learning based runtime solution that makes intelligent scheduling decisions for OpenMP kernels using prediction results from a machine learning model. CogR improves previous work on two fronts. We incorporate the syntactic structures of programs to generate more expressive representation for programs than non-structured representation, and provide an end-to-end runtime solution that communicates with the trained model for real-time predictions. For my future work, I look towards further exploiting program and domain knowledge to improve machine-learning solutions for compilers and runtime in terms of model construction, search space exploration, and input generation.