Typed Architecture: Architectural Support for Lightweight Scripting

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Typed Architecture: Architectural Support for Lightweight Scripting



Jae W. Lee is an associate professor in the Department of Computer Science and Engineering at Seoul National University (SNU), Korea. His research areas include computer architecture, compilers, and parallel computing, and he has co-authored more than 50 research papers in these areas. His work has been recognized with two test-of-time awards (IEEE VLSI Symposium 2017, ACM ASPLOS 2014), and several top/highlights papers (ACM ASPLOS 2017, IEEE PACT 2010, IEEE/ACM MICRO 2010). Before joining SNU, he was an assistant professor of Semiconductor Systems Engineering at Sungkyunkwan University (SKKU), Korea. Prior to that, he was a research associate at Princeton University, and a researcher and engineer at Parakinetics, Inc. (Princeton, NJ), where he conducted research on multicore software optimization. He received his M.S. degree in Electrical Engineering from Stanford University and Ph.D. degree in Computer Science from MIT.


Dynamic scripting languages are becoming more and more widely adopted not only for fast prototyping but also for developing production-grade applications. They provide high-productivity programming environments featuring high levels of abstraction with powerful built-in functions, automatic memory management, object-oriented programming paradigm and dynamic typing. However, their flexible, dynamic type systems easily become the source of inefficiency in terms of instruction count, memory footprint, and energy consumption. Besides, the bytecode dispatch loop incurs significant performance cost due to redundant computation and hard-to-predict indirect jumps. This overhead makes it challenging to deploy these high-productivity programming technologies for production, especially on emerging single-board computers for IoT applications. In this talk I will present Typed Architecture, a high-efficiency, low-cost execution substrate for dynamic scripting languages, where each data variable retains high-level type information at an ISA level. Typed Architecture calculates and checks the dynamic type of each variable implicitly in hardware, rather than explicitly in software, hence significantly reducing instruction count for dynamic type checking. To reduce the recurring cost of bytecode dispatch, I also introduce Short-Circuit Dispatch (SCD), an architectural extension that enables fast, hardware-based bytecode dispatch with fewer instructions. Our evaluation using a fully synthesizable RISC-VRTL design on FPGA demonstrates that Typed Architecture augmented with SCD achieves geomean speedups of 24.3% and 19.8% with maximum speedups of 65.0% and 63.5% for two production-grade scripting engines for Lua and JavaScript, respectively.