Modular hardware design of pipelined circuits with hazards

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Modular design is critical in reducing hardware designer’s cognitive load and development cost. However, it is challenging to modularize high-performance pipelined circuits with structural, data, and control hazards because their resolution—stalling, and bypassing, and discard-and-restarting—introduce cross-stage dependencies. The dependencies could potentially mandate monolithic control logic and create combinational loops, hindering modular design. An effective method to modularize pipelined circuits is valid-ready interfaces, but they apply to a relatively simple form of pipelined circuits only with structural hazards.

We propose hazard interfaces, a generalization of valid-ready interfaces that can modularize pipelined circuits not only with structural but also with data and control hazards. The key idea is enveloping the cross-stage dependencies within interfaces. We also design combinators for hazard interfaces in the style of map-reduce that facilitate decomposition of control logic. We implement a compiler (to synthesizable Verilog) for a prototype language supporting hazard interfaces and combinators, and design a sound and efficient type checker that proves the absence of combinational loops. With case studies on 5-stage RISC-V CPU core and 100 Gbps Ethernet NIC, we demonstrate that hazard interfaces indeed facilitate modular design while incurring no noticeable cost in performance, power, and area over reference designs in Chisel and Verilog.

Jeehoon Kang has been an Associate/Assistant Professor in the School of Computing at KAIST since 2019. His main interest lies in understanding systems from the perspective of programming languages, especially in designing and verifying concurrent programs for highly parallel tasks, which will become increasingly important in the era of artificial intelligence and big data. Kang earned his Ph.D. from Seoul National University in 2019. He has published 18 papers at top-tier international conferences designated by KIISE and has received several awards, including the Whang Kyu-Young Career Award (2023), a POPL Distinguished Paper Award (2022), a PLDI Distinguished Paper Award (2017). Kang has led the development as the main maintainer of the Rust concurrency library Crossbeam and has written compilers for FuriosaAI, a fabless startup designing cutting-edge AI chips.