Accelerating deep learning: from hardware to software(Eng.)

Abstract

 The recent breakthrough in deep learning has accelerated the innovation of artificial intelligence in various domains such as autonomous vehicles, surveillance, medical diagnosis, and smart agents. The advance of deep learning is at the cost of enormous computing power to process massive data in a very short time. Traditional computer architecture has shown limited success in meeting this computing demand due to its support for general applications. Therefore, accelerators customized specifically for deep learning has emerged as a promising solution, but with a challenge of enhancing both computational efficiencies as well as the generality in applications.

In this talk, we review the recent evolution of deep learning accelerators across the stack from hardware to software to address this challenge. We first introduce recent innovations in deep learning algorithms to reduce the computational complexity of deep learning. Then we introduce a set of hardware architectures that exploit the algorithmic innovation in their customized architectures. Lastly, we discuss a challenge in the software of effectively mapping the computation-efficient algorithms into the customized hardware for high utilization and generality, then we introduce a few recent efforts on it.

 Biography

Jungwook Choi is an assistant professor at Hanyang University in South Korea. His main research interest is the efficient implementation of deep learning algorithms. He received the B.S. and M.S. degree in Electrical and Computer Engineering from Seoul National University, South Korea, in 2008 and 2010, respectively, and his Ph.D. in Electrical and Computer Engineering from the University of Illinois at Urbana-Champaign, the US, in 2015. He worked at the IBM T.J. Watson Research as a Research Staff Member from 2015 to 2019. He has received several research awards such as DAC 2018 best paper award and has been actively contributed to the academic activities, such as Technical Program Committee of DATE 2018-2020(co-chair) and DAC 2018-2020, Technical Committee (DiSPS) in IEEE Signal Processing Society, and reviewers of NeurIPS19, TPAMI, and JETCAS.